1. Field of the Invention
The present invention relates to a package for an integrated circuit.
2. Description of Related Art
Integrated circuits are typically housed within a package that is soldered to a printed circuit board. The package typically has a plurality of bond pads that are connected to corresponding output pads of the integrated circuit. The bond pads are coupled to external package contacts by internal power/ground planes, signal routing traces and vias. The vias interconnect the bond pads and contacts to the various internal routing layers within the substrate of the package.
FIG. 1 shows a power/ground plane 2 of the prior art which has a plurality of vias 4 that provide interconnect to other layers of the package. The plane 2 has a large central opening 6 of dielectric material which separates the vias 4 from the conductive buss material. The dielectric space prevents the vias from shorting to the conductive plane. The plane may contain traces 8 that couple some of the vias 4 to the power/ground buss.
The internal routing of the package creates switching noise that limits the speed of the integrated circuit. The switching noise can be particularly critical to a highly functional integrated circuit such as a microprocessor. It is therefore desirable to minimize the switching noise created by the substrate.
Switching noise is a function of the effective inductance and capacitance of the substrate. Noise will decrease with an increase in the substrate capacitance. The large dielectric opening increases the resistance and decreases the capacitance of the package. It is desirable to provide a flip chip package which increases the capacitance and minimizes the noise created by the package.